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Memory architecture
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#	Item
21	Skippy: Enabling Long-Lived Snapshots of the Long-Lived Past Ross Shaull, Liuba Shrira, Hao Xu Department of Computer Science, Brandeis University Waltham, Massachusetts, USA {rshaull,liuba,hxu}@cs.brandeis.edu Add to Reading List Source URL: www.cs.brandeis.edu Language: English - Date: 2007-11-22 16:42:50 Software Computing Virtual memory Computer architecture Backup Persistence Snapshot Computer data storage Skippy Page table Copy-on-write
22	L8: Memory Models CSE 452 Winter 2016 “There are only two hard things in computer science: cache invalidation and naming things.”  - Phil Karlton Add to Reading List Source URL: courses.cs.washington.edu Language: English - Date: 2016-01-22 21:17:29 Computing Computer architecture Transaction processing Concurrency control Consistency model Cache coherency Sequential consistency Linearizability Cache Eventual consistency Sync Weak consistency
23	Minerva: Accelerating Data Analysis in Next-Generation SSDs Arup De⇤† Maya Gokhale† Add to Reading List Source URL: mesl.ucsd.edu Language: English - Date: 2013-08-03 18:53:16 Computer hardware Computing Computer data storage Computer memory Non-volatile memory Computer architecture Peripheral Component Interconnect Solid-state drive Direct memory access Cell Flash memory PCI Express
24	Design of Parallel and High Performance Computing HS 2014 Torsten Hoefler, Markus P¨ uschel Department of Computer Science ETH Zurich Add to Reading List Source URL: spcl.inf.ethz.ch Language: English - Date: 2014-10-09 06:28:40 Cache coherency Computing Computer hardware Computer architecture MESI protocol Cache Cache memory CPU cache
25	Dynamic Thread Mapping Based on Machine Learning for Transactional Memory Applications Márcio Castro1, Luís Fabrício Wanderley Góes,2 Luiz Gustavo Fernandes,3 Jean-François Méhaut1 Add to Reading List Source URL: www.gsd.inesc-id.pt Language: English - Date: 2012-04-18 12:46:07 Computing Concurrency control Transaction processing Computer memory Computer architecture Parallel computing Transactional memory Thread Multi-core processor
26	The Semantics of x86-CC Multiprocessor Machine Code Susmit Sarkar1 Scott Owens1 Tom Ridge1 Add to Reading List Source URL: www0.cs.ucl.ac.uk Language: English - Date: 2012-09-10 07:41:01 Computing Computer architecture Software engineering X86 architecture Computer memory Low-level programming language Spinlock X86 Assembly language Memory barrier Memory ordering Exit
27	Microsoft Word - NLA-monographdoc Add to Reading List Source URL: foibg.com Language: English - Date: 2015-06-14 11:37:42 Computing Computer memory Data types Computer architecture Primitive types Data management Memory address Data Pointer Address space Array data structure Reference
28	Kurzvorstellung ULIX ULIX und Didaktik der Betriebssysteme Hans-Georg Eßer Universit¨at Erlangen-N¨ Add to Reading List Source URL: hgesser.de Language: English - Date: 2011-07-21 15:54:20 Memory management Computing Software Memory segmentation Virtual memory Paging University of Erlangen-Nuremberg Didaktik Computer architecture
29	spcl.inf.ethz.ch @spcl_eth Polly-ACC: Transparent Compilation to Heterogeneous Hardware Tobias Grosser, Torsten Hoefler Add to Reading List Source URL: htor.inf.ethz.ch Language: English - Date: 2016-06-01 08:57:33 GPGPU Computer architecture Computing Graphics hardware Parallel computing Computer engineering Graphics processing unit Virtual reality Compute kernel General-purpose computing on graphics processing units CUDA Pinned memory
30	1 FROM RING3 TO RING0: EXPLOITING THE XEN X86 INSTRUCTION EMULATOR Andrei Vlad Luțaș Bitdefender Add to Reading List Source URL: labs.bitdefender.com Language: English - Date: 2016-01-22 04:06:36 Computer architecture Computing X86 architecture Interrupts X86 instructions Memory management Interrupt descriptor table Task state segment Global Descriptor Table Interrupt flag X86 Interrupt

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